Japanese Patent Application No. 2001-168374, filed on Jun. 4, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor storage device constructed of memory cells each including two nonvolatile memory elements which are controlled by one word gate and two control gates.
Known as a nonvolatile semiconductor device is the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type wherein the gate insulator layer between a channel and a gate is formed of a stacked structure consisting of a silicon oxide film, a silicon nitride film and a silicon oxide film, and wherein electric charges are trapped in the silicon nitride film.
The MONOS type nonvolatile semiconductor storage device is disclosed in a publication, Y. Hayashi, et al.: 2000 Symposium on VLSI Technology, Digest of Technical Papers, p.122 to p.123. The publication teaches a MONOS flash memory cell including two nonvolatile memory elements (also termed xe2x80x9cMONOS memory elements or cellsxe2x80x9d) which are controlled by one word gate and two control gates. That is, one flash memory cell has two trap sites for charges.
A plurality of MONOS flash memory cells each having such a structure are arranged in each of a row direction and a column direction, thereby to construct a memory cell array region.
Two bit lines, one word line and two control gate lines are required for driving the MONOS flash memory cell. In driving a large number of memory cells, however, such lines can be connected in common in a case where even the different control gates are set at the same potential.
Here, when the bit line is shared by the large number of memory cells, the load thereof enlarges, and the high speed drive of the storage device is impossible. Moreover, the storage device dissipates more electric power and becomes unsuited to portable equipment etc.
These problems can be solved in such a way that the bit lines are divided into a main bit line and sub bit lines, and that only the sub bit line connected to the memory cell within a block area to-be-selected is connected to the main bit line through a bit line selection transistor.
With this method, however, the gate voltage of the bit line selection transistor must be boosted in order that current to flow through the bit line may be ensured especially as in a data read mode.
The present invention may provide a nonvolatile semiconductor storage device in which a control voltage for a bit line selection switching element is lowered by analyzing the operation of a read operation from memory cells.
One aspect of the present invention relates to a nonvolatile semiconductor storage device comprising:
a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting with each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates;
a plurality of sub bit lines which extend in the first direction and are disposed in a plurality of block areas formed by dividing the memory cell array region in the first direction, each of the sub bit lines being connected with the first nonvolatile memory element of one of two the memory cells adjacent each other in the second direction and the second nonvolatile memory element of the other of the two memory cells;
a plurality of main bit lines which are formed extending over the plurality of block areas arranged in the first direction, each of the main bit lines being connected in common to the plurality of sub bit lines respectively disposed in the block areas arranged in the first direction;
a plurality of bit line selection switching elements which are respectively disposed at connection points between the main bit lines and the sub bit lines, and select connection or non-connection based on a control voltage; and
a bit line selection driver which supplies the control voltage to the bit line selection switching elements.
The plurality of bit line selection switching elements include a first group of bit line selection switching elements and a second group of bit line selection switching elements, respectively connected with every second line among the sub bit lines arranged in the second direction.
The bit line selection driver include a first bit line selection driver which supplies a first control voltage to the first group of bit line selection switching elements, and a second bit line selection driver which supplies a second control voltage to the second group of bit line selection switching elements.
The first bit line selection driver supplies the first group of bit line selection switching elements with the first control voltage that is set to be lower than the second control voltage when data is read out of one of the first and second nonvolatile memory elements, and a bit line selection switching element connected to the sub bit line serving as a source of selected one of the memory cells is included in the first group of bit line selection switching elements.
The second bit line selection driver supplies the second group of bit line selection switching elements with the second control voltage that is set to be lower than the first control voltage when data is read out of the other of the first and second nonvolatile memory elements, and a bit line selection switching element connected to the sub bit line serving as a source of selected one of the memory cells is included in the second group of bit line selection switching elements.
According to the one aspect of the present invention, in a data read mode or a data program mode, only the sub bit lines selected by the bit line selection switching elements are connected to the main bit lines, so that the loads of the bit lines are reduced to permit a high speed operation.
Besides, when data is read from a selected cell (selected one of first and second nonvolatile memory elements), current flows through the sub bit line which serves as a drain in the memory cell including the selected cell, and hence, the control voltage of the bit line selection switching element arranged midway of the sub bit line needs to be heightened.
On the other hand, the voltage of the bit line connected to the source of the memory cell becomes close to 0V. Therefore, the back gate of the bit line selection transistor connected to the sub bit line serving as the source exerts little influence, and the control voltage of this transistor need not be made so high as the control voltage on the drain side. In this manner, the control voltage of one bit line selection switching element can be made low, so that the load of a booster circuit (charge pump) for generating the high voltage can be lightened.
Between the first and second control voltages, a lower voltage may be set at a supply voltage, and a higher voltage may be set at a voltage generated by boosting the supply voltage. The current on the drain side can be ensured by employing the supply voltage as the low voltage, and the low voltage need not to be generated by boosting.
Data may be read out in a reverse read mode by using a source which is the sub bit line connected to a selected element between the first and second nonvolatile memory elements, the data being read out of the selected element, and by using a drain which is the sub bit line connected to an unselected element between the first and second nonvolatile memory elements, the data not being read out of the unselected element.
Alternatively, data may be read out in a forward read mode by using a drain which is the sub bit line connected to a selected element between the first and second nonvolatile memory elements, the data being read out of the selected element, and by using a source which is the sub bit line connected to an unselected element between the first and second nonvolatile memory elements, the data not being read out of the unselected element.
The nonvolatile semiconductor storage device may further comprise a bit line selection voltage control circuit which supplies the first and second control voltages to the first and second bit line selection drivers, respectively.
The nonvolatile semiconductor storage device may further comprise a predecoder which predecodes an address signal for specifying one of the first and second nonvolatile memory elements from which data is to be read out. In this case, the bit line selection voltage control circuit may set each of the first and second control voltages at one of the lower voltage and the higher voltage in accordance with a predecoded output from the predecoder.
Each of the first and second bit line selection drivers may be disposed in respective one of the plurality of block areas arranged in the first direction. In this case, the bit line selection voltage control circuit may supply the first and second control voltages to the first and second bit line selection drivers, respectively.
The nonvolatile semiconductor storage device may further comprise a global decoder which collectively selects the block areas arranged in the second direction, based on the predecoded output delivered from the predecoder. In this case, the first and second bit line selection drivers may supply the first and second control voltages to the first and second groups of bit line selection switching elements, respectively, when a decoded output from the global decoder is active.
The first and second bit line selection drivers may be respectively arranged in local driver areas which are adjacent to the block areas in the second direction.
In this case, an odd-numbered block area and an even-numbered block area among the block areas arranged in the second direction may be disposed adjacent each other between two of the local driver areas among the local driver areas arranged in the second direction.
On this occasion, the first group of bit line selection switching elements and the second groups of bit line selection switching elements may respectively be connected to every second line among the sub bit lines arranged in the second direction in the odd-numbered block area and the even-numbered block area.
The first bit line selection driver, which drives the first groups of bit line selection switching elements, may be disposed in one of the local driver areas which is adjacent to the odd-numbered block area, and the second bit line selection driver, which drives the second groups of bit line selection switching elements, may be disposed in another of the local driver areas which is adjacent to the even-numbered block area.
Each of the first and second nonvolatile memory elements may include an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O), as a trap site for electric charges. However, the nonvolatile memory elements are not limited to such as structure, and other structures can be adopted.